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Enterprise AI Analysis: Mixed-Precision Performance Portability of FFT-Based GPU-Accelerated Algorithms for Block-Triangular Toeplitz Matrices

Enterprise AI Analysis

Mixed-Precision Performance Portability of FFT-Based GPU-Accelerated Algorithms for Block-Triangular Toeplitz Matrices

This analysis explores how mixed-precision computing and performance portability can revolutionize scientific HPC workflows, specifically for FFT-based GPU-accelerated algorithms for Block-Triangular Toeplitz Matrices.

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The study highlights the critical need for performance portability in HPC, given the diverse hardware landscape (AMD, NVIDIA, Intel). It showcases an 'on-the-fly' hipification framework that seamlessly converts CUDA code to HIP at compile time, enabling applications like FFTMatvec to run efficiently on AMD GPUs without code refactoring. This approach maintains a single CUDA source codebase while leveraging vendor-specific optimizations for enhanced performance, even integrating custom kernels into rocBLAS.

A dynamic mixed-precision framework is introduced for FFTMatvec, allowing algorithms to selectively use single (FP32) or double (FP64) precision based on desired error tolerance. This strategy capitalizes on the higher throughput of GPUs for lower-precision workloads, achieving significant speedups while maintaining accuracy. A Pareto front analysis guides the optimal precision configuration, identifying that FFT and SBGEMV in single precision yield the best balance of speedup and error.

Key performance optimizations for AMD GPUs were integrated directly into the open-source rocBLAS library. Specifically, an optimized strided batched GEMV (SBGEMV) kernel addresses performance reductions in conjugate transpose matvecs for short, wide matrices (Nd << Nm). This custom kernel, utilizing tiling, 2D thread blocks, vectorized data loads, and pipelining, achieved significantly higher memory bandwidth, resolving a critical bottleneck for F* matvecs.

The performance-portable, mixed-precision FFTMatvec application was successfully scaled to 4,096 GPUs on the OLCF Frontier supercomputer. Communication-aware partitioning was used to optimize the 2D processor grid shape. At this scale, the application computed a matvec with over 20 billion parameters in approximately 0.11 seconds, demonstrating its capability for extreme-scale scientific computing for problems like Bayesian inverse problems and optimal sensor placement.

Enterprise Process Flow

CUDA Source Code
Hipify (On-The-Fly Conversion)
HIP Source Code
AMD GPU Compilation
Optimized Execution on AMD GPUs

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